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Semicon India 2.0 was approved in July 2026 with a ₹1,27,500 crore outlay, scaling up the ₹76,000 crore Semicon 1.0 programme across six pillars — chip design, equipment and materials, fabrication, advanced packaging, R&D and talent.
Twelve semiconductor projects have been approved across six states with investment commitments above ₹1.64 lakh crore; three facilities have already begun commercial production.
The IndiaAI Mission, with an outlay of about ₹10,372 crore, had expanded shared compute to more than 45,000 GPUs as of June 2026, and 237 projects had used 93.18 lakh subsidised GPU hours by August 2026.
Twenty indigenous foundation model proposals — 12 large multimodal models and 8 small language models — were selected from 506 applications; AI Kosh hosted over 14,000 datasets and 331 AI models as of July 2026.
India was ranked third globally in the Stanford Global AI Vibrancy Report 2025 and joined the Pax Silica coalition on resilient silicon supply chains at the India AI Impact Summit 2026.
Build a domestic semiconductor and display manufacturing and design ecosystem, and act as the nodal agency implementing the semiconductor schemes
Key: Launched in 2021 under the Ministry of Electronics and Information Technology with a ₹76,000 crore outlay; set up as an independent business division within the Digital India Corporation with administrative and financial autonomy. It covers silicon fabs, display fabs, compound semiconductor/silicon photonics/sensor fabs, packaging (ATMP/OSAT) and design.
Move from building an ecosystem to global ecosystem leadership
Key: ₹1,27,500 crore outlay approved in July 2026, organised around six pillars: chip design, semiconductor equipment and materials, fabrication facilities, advanced packaging, research and development, and talent development. It also adds support for semiconductor IP, chip and system designs.
Support domestic companies, startups and MSMEs across semiconductor design — integrated circuits, chipsets, systems-on-chip, systems and IP cores
Key: Launched in December 2021 and notified in the Gazette on 21 December 2021; C-DAC is the nodal implementing agency. It offers financial incentives, access to advanced design tools and prototyping support. As per this release, 24 design projects and 105 startups/MSMEs have been supported.
Build the chip-design workforce by putting industry-grade design tools inside academic institutions
Key: Electronic Design Automation tools deployed in 320 academic institutions with over 68,000 students trained; 211 chips taped out by 75 institutions by April 2026, of which 7 were fabricated at nodes including 12 nm.
Build a sovereign, inclusive AI ecosystem — compute, datasets, models, applications, skills, startup finance and safe/trusted AI
Key: Approved on 7 March 2024 with an outlay of ₹10,371.92 crore under MeitY, structured around pillars including AI Compute Capacity, Innovation Centre, Datasets Platform, Application Development Initiative, FutureSkills, Startup Financing and Safe & Trusted AI.
Serve as the national datasets and models platform for AI developers and researchers
Key: The datasets platform pillar of the IndiaAI Mission; hosted over 14,000 datasets and 331 AI models as of July 2026.
Create research, translation and entrepreneurship capacity in cyber-physical systems
Key: Has established 25 Technology Innovation Hubs at leading academic institutions covering AI, robotics, cybersecurity, quantum technologies and other emerging fields.
Seed and scale scientific and industrial R&D in quantum technologies
Key: Approved by the Union Cabinet on 19 April 2023 at a total cost of ₹6,003.65 crore for 2023-24 to 2030-31, implemented by the Department of Science and Technology. Deliverables include quantum computers with 50-1,000 physical qubits in eight years and satellite-based quantum communication over 2,000 km.
Nodal agency for implementing India's semiconductor and display manufacturing and design schemes; an independent business division within the Digital India Corporation with administrative and financial autonomy
Premier R&D organisation of MeitY; nodal agency for the Design Linked Incentive Scheme and developer of the PARAM series of supercomputers (beginning with PARAM 8000 in 1991)
India's largest AI supercomputing system, installed at C-DAC Pune; it was ranked 75th in the 61st edition of the Top 500 global supercomputing list announced at ISC 2023
Implements the National Quantum Mission and hosts NM-ICPS Technology Innovation Hubs
A fab turns raw silicon wafers into functioning integrated circuits using photolithography at a given process node (12 nm, 28 nm and so on) — it is the most capital-intensive stage. ATMP stands for Assembly, Testing, Marking and Packaging: it takes finished wafers from a fab, cuts and encases the chips, wires them, marks and tests them. OSAT — Outsourced Semiconductor Assembly and Test — is the same work offered as a third-party service rather than done in-house. Display fabrication is a separate line making flat and flexible screens. Design sits before all of this and uses Electronic Design Automation (EDA) software to lay out, simulate and verify a chip before a single wafer is touched; a completed design sent for manufacturing is called a 'tape-out'. India's approved projects span all of these categories, and Micron's Sanand plant in Gujarat — approved by the Union Cabinet on 22 June 2023 with a capital investment of ₹22,516 crore (about USD 2.75 billion) under the Modified ATMP Scheme — is the back-end example.
Simple Analogy: A fab is the printing press that makes the pages; ATMP/OSAT is the bindery that trims, covers and quality-checks the book; design with EDA tools is the manuscript and proofreading that must be finished before anything is printed.
| Aspect | Semicon India 1.0 | Semicon India 2.0 |
|---|---|---|
| Year | Launched 2021 | Approved July 2026 |
| Outlay | ₹76,000 crore | ₹1,27,500 crore |
| Stated aim | Lay the foundation of a semiconductor ecosystem | Scale the foundation into global ecosystem leadership |
| Structure | Support across chip design, fabrication, packaging, testing, equipment, materials and talent | Six pillars: chip design; equipment and materials; fabrication; advanced packaging; R&D; talent development |
| Design focus | Design Linked Incentive and Chips to Startup support | Adds support for semiconductor IP, chip and system designs |
C-DAC established after supercomputer exports to India were denied; later the nodal agency for the DLI Scheme
India Semiconductor Mission launched with a ₹76,000 crore outlay under MeitY
Design Linked Incentive Scheme notified in the Gazette of India
Union Cabinet approves the National Quantum Mission (₹6,003.65 crore, 2023-24 to 2030-31)
Union Cabinet approves Micron's semiconductor assembly and test facility at Sanand, Gujarat (₹22,516 crore)
IndiaAI Mission approved with an outlay of ₹10,371.92 crore
211 chips taped out by 75 institutions under the design programmes; 7 fabricated
India AI Impact Summit 2026 held; declaration adopted by 92 countries and organisations; India joins the Pax Silica coalition
Semicon India 2.0 approved with a ₹1,27,500 crore outlay
Both NQM (DST, ₹6,003.65 crore, approved 19 April 2023) and the semiconductor programme rest on the same bottleneck — advanced fabrication and specialised processors. NM-ICPS Technology Innovation Hubs cover quantum technologies alongside AI and robotics.
Chip fabrication and advanced packaging depend on materials whose supply is geopolitically concentrated, which is why 'equipment and materials' is a standalone pillar of Semicon 2.0 and why India joined the Pax Silica coalition.
Data centre capacity rose from 375 MW in 2020 to about 1,575 MW, and AI compute is energy-intensive — linking this topic directly to India's power capacity expansion and non-fossil energy targets.
ISM is not a separate statutory body but an independent business division inside the Digital India Corporation — a favourite distinction in questions about how the mission is actually constituted.
GS Paper 3 > Science and Technology > Indigenisation of Technology and Developing New Technology
General Awareness > Government Schemes and Missions
General Awareness > Economy and Industrial Policy
Semiconductors and AI missions have appeared repeatedly in Prelims and Mains since 2022 and are near-certain recurring themes
The point at which a finished chip design is sent for manufacturing; 211 tape-outs by 75 institutions had been recorded by April 2026.
Software used to design, simulate, verify and optimise chips before manufacture, catching errors and cutting design time and cost.
Assembly, Testing, Marking and Packaging — the back-end stage that turns fabricated wafers into usable, tested chips.
Outsourced Semiconductor Assembly and Test — ATMP work provided as a third-party service to chipmakers.
Graphics Processing Unit, a specialised processor for graphics and data-intensive computing; the unit in which IndiaAI's shared compute is measured.
The manufacturing generation of a chip, expressed in nanometres — India has fabricated chips at nodes including 12 nm.