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The Government of India notified the Semicon 2.0 scheme on 31 August 2026, the second phase of the Semicon India Programme, with a fiscal outlay of Rs 1,27,500 crore.
The scheme is built around six pillars - design, machines and materials, fabrication units, ATMP and OSAT facilities, research and development, and talent development - spread across ten categories.
Silicon wafer fabs with a minimum investment of Rs 20,000 crore get central fiscal support of 40 per cent of eligible capital expenditure; compound, display and other specialised fabs get 35 per cent.
On the design side, the Deployment-Linked Incentive reimburses 9 per cent of net sales for up to five years, capped at Rs 30 crore per application and Rs 120 crore per company, and startups and Indian- or OCI-owned companies can apply.
A high-level expert panel co-chaired by the Principal Scientific Adviser and the National Security Adviser will identify strategic chips of national interest; the government expects about Rs 4 lakh crore of investment and Rs 2 lakh crore of production, and targets the training of 1,00,000 more semiconductor engineers.
A chip passes through four broad stages. Design turns a specification into a circuit layout, and is capital-light but talent-heavy - India already does a large share of the world's design work. Fabrication etches that layout onto silicon wafers in a fab, the most capital-intensive step by far, which is why the scheme offers 40 per cent of capital expenditure and still sets a Rs 20,000 crore floor. ATMP and OSAT come next: the wafer is cut into individual dies, which are assembled, tested, marked and packaged - less capital-hungry, faster to build and therefore where a new entrant usually starts. Running underneath all three is the equipment and materials layer - lithography machines, ultra-pure chemicals, specialty gases - which almost no country supplies alone. Semicon 2.0 puts money into all four, which is the substantive change from the first phase.
Simple Analogy: Design is drawing the building plan, fabrication is casting the structure, ATMP and OSAT are the fitting-out and quality check before handover, and machines and materials are the cranes and cement that everyone else depends on.
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A plant where integrated circuits are manufactured on silicon wafers through photolithography and related processes; the most capital-intensive stage of chip making.
Assembly, testing, marking and packaging - the back-end stage in which finished wafers are cut into dies and packaged into usable chips.
Outsourced semiconductor assembly and test - a company that performs ATMP work on contract for chip designers and manufacturers.
Under Semicon 2.0, a reimbursement of 9 per cent of net sales for up to five years for new intellectual property, chips and systems-on-chip that have had no prior sales.