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Notifications for all six pillars of the Semicon 2.0 Scheme were issued, with Union Minister for Electronics and Information Technology Ashwini Vaishnaw setting out the government's plan for the next phase of India's semiconductor ecosystem.
The six pillars — Design; Machines and Materials; Setting up more Fabs; Strengthening the ATMP/OSAT industry; Research and Development; and Talent Development — cover 10 categories in all and extend fiscal and infrastructure support across the whole value chain.
The India Semiconductor Mission (ISM) is the nodal agency: it will invite applications, carry out technical and financial appraisal, recommend applicants and oversee implementation, with C-DAC assisting on the design and deployment categories.
Projects will generally run up to six years, the scheme stays open for applications for three years, and a mid-term assessment follows after three years of implementation.
Vaishnaw said India met its target of 85,000 semiconductor engineers in four years against a ten-year timeline and has set a fresh target of one lakh more, that students from Tier-II and Tier-III cities have designed over 250 chips, and that the ecosystem is expected to create 50,000-60,000 direct jobs.
The first phase — approved by the Union Cabinet in 2021 with an outlay of ₹76,000 crore to develop a sustainable semiconductor and display ecosystem in India.
Key: It offered fiscal support of up to 50 per cent of project cost for silicon fabs, compound semiconductor facilities, assembly and testing units and chip design. By December 2025 it had approved 10 projects worth about ₹1.60 lakh crore across six states.
The successor programme, notified by MeitY with an outlay of ₹1,27,500 crore — more than 1.6 times the first phase — to extend support from chip design and fabrication through packaging to equipment, materials, R&D and talent.
Key: Approved by the Union Cabinet on 15 July 2026 and structured as six pillars covering 10 categories. Its most significant addition over the first phase is Pillar 2 (Machines and Materials) — support for the equipment and materials layer, the part of the value chain India had no scheme for.
To offset the disabilities faced by India's domestic semiconductor design industry and build a base of Indian chip-design companies.
Key: Launched in December 2021 under the Semicon India Programme, with C-DAC as nodal agency. It gives a product design incentive of up to 50 per cent of eligible expenditure subject to a ceiling of ₹15 crore per application, plus a deployment-linked incentive of 6 to 4 per cent of net sales turnover subject to a ceiling of ₹30 crore per application. Under Semicon 2.0, deployment-linked support sits inside Pillar 1.
To build the human capital layer — industry-ready chip-design manpower at B.Tech, M.Tech and PhD level across academic institutions.
Key: Launched by MeitY in 2022 with an outlay of ₹250 crore over five years and a target of 85,000 trained personnel. That is the target Vaishnaw said was met in four years rather than the planned ten. C2S is the predecessor of Semicon 2.0's Pillar 6.
To give start-ups and academic institutions centralised access to expensive chip-design and fabrication services they could not otherwise afford.
Key: Set up at C-DAC as a one-stop centre providing access to Electronic Design Automation (EDA) tools, used by roughly one lakh engineers and students across some 400 organisations.
A semiconductor fab is the front end: it etches circuits onto a silicon wafer, an extraordinarily capital-intensive and precision-heavy process. What comes out is a wafer of finished but unusable dies. The back end — Assembly, Testing, Marking and Packaging (ATMP) — cuts those dies, mounts them, wires them, seals them in a package and tests them. When a company does this back-end work for other firms rather than for its own chips it is called an OSAT, an Outsourced Semiconductor Assembly and Test provider; ATMP describes the process, OSAT the business model, which is why Indian policy documents name them together. A third category cuts across both: compound semiconductors are made not from silicon alone but from combinations such as silicon carbide or gallium nitride, which handle high voltage, high frequency and high temperature far better than silicon and are therefore central to electric vehicles, power electronics, defence radar and 5G. Semicon 2.0 gives fabs, ATMP/OSAT and compound-semiconductor fabs their own categories because their economics, scale and technology are entirely different, and a single incentive rate would fit none of them.
Simple Analogy: The fab is the printing press that produces the sheets. ATMP/OSAT is the bindery that cuts, sews and covers them into a usable book. A compound-semiconductor fab is a different press altogether — one built for materials that tolerate heat and voltage that would destroy ordinary silicon.
The nodal agency for Semicon 2.0 and for the earlier Semicon India Programme. It invites applications, undertakes technical and financial appraisal, recommends applicants, disburses fiscal support and oversees implementation. It may also announce semiconductor deep-tech awards from 2026.
The parent ministry. It notified Semicon 2.0, makes the budgetary provisions for fiscal support, and runs the DLI and C2S schemes through its agencies.
MeitY's premier R&D organisation. It is the nodal agency implementing the Design Linked Incentive scheme, hosts the ChipIN Centre, and may assist ISM in implementing Semicon 2.0's design and deployment categories.
The 85,000-engineer figure Vaishnaw cited is the target of the Chips to Startup programme, launched in 2022 with ₹250 crore over five years. It was met in four years, and Pillar 6 of Semicon 2.0 now carries the next target of one lakh more.
Front-end fabrication is the headline, but India's comparative advantage has been in design — the DLI scheme, the ChipIN Centre's EDA access for about one lakh engineers across 400 organisations, and the 250-plus chips designed by students from Tier-II and Tier-III cities. Pillar 1 splits design three ways, including a separate strategic-priorities category.
Pillar 3's second category covers compound semiconductors, photonics and sensors including MEMS. Silicon carbide and gallium nitride devices are what make efficient EV powertrains, fast chargers, 5G base stations and modern radar possible — which is why they get a category of their own rather than being folded into silicon fabs.
No country has built a durable chip industry while importing every tool and chemical it uses. Pillar 2 is Semicon 2.0's answer to that, and it is the clearest structural difference from the 2021 programme.
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India's semiconductor mission has appeared in UPSC Prelims and Mains, SSC and banking general awareness in every cycle since 2022, and a fresh scheme notification makes 2026-27 coverage near-certain.
MeitY's second-phase semiconductor scheme, with a ₹1,27,500 crore outlay, six pillars and 10 categories; approved by the Cabinet on 15 July 2026 and pillar notifications issued on 31 August 2026.
The nodal agency under MeitY that appraises, recommends, funds and oversees semiconductor projects.
Assembly, Testing, Marking and Packaging — the back-end stage that turns finished wafers into usable packaged chips.
Outsourced Semiconductor Assembly and Test — a firm that performs ATMP work for other companies' chips.
A semiconductor made from a combination of elements, such as silicon carbide or gallium nitride, suited to high-voltage, high-frequency and high-temperature use.
Design Linked Incentive — launched December 2021, implemented by C-DAC, offering up to 50 per cent of eligible design expenditure (ceiling ₹15 crore) and a deployment-linked incentive on net sales turnover (ceiling ₹30 crore).
MeitY's 2022 capacity-building programme, ₹250 crore over five years, targeting 85,000 industry-ready chip-design personnel.
A single chip integrating processor, memory and other subsystems that would otherwise be separate components.