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The fifth edition of SEMICON India will be held from 17 to 19 September 2026 at Yashobhoomi, the India International Convention and Expo Centre in Dwarka, New Delhi, and will be inaugurated by the Prime Minister on 17 September.
It is organised jointly by the India Semiconductor Mission under the Ministry of Electronics and Information Technology and SEMI, the global semiconductor industry association, on the theme 'Silicon to Systems: Building the Ecosystem'.
Twelve projects have been approved under Semicon 1.0, three of which have begun commercial production, and the Union Cabinet has since approved the next phase, Semicon 2.0, built on six major pillars.
On the design side, state-of-the-art tools have been provided to more than 332 academic institutes and 105 start-ups, and 24 start-ups have been approved under the Design Linked Incentive scheme.
The exhibition is expected to draw over 500 exhibitors including 240-plus international companies, 150-plus international speakers, delegations from more than 40 countries, six country pavilions and ten State government pavilions across 15,000 square metres.
A fabrication plant, or fab, is where the chip itself is created: silicon wafers are patterned layer by layer through photolithography, etching and deposition in a cleanroom, and the process is defined by its node size. Fabs are the most capital-intensive and technologically demanding link in the chain. Once wafers are made, the individual dies must be cut, mounted, wired and sealed, and then tested — that is Assembly, Testing, Marking and Packaging, or ATMP. When a company does that work for other firms' chips rather than its own, the same activity is called Outsourced Semiconductor Assembly and Test, or OSAT. India's programme deliberately began at the back end: packaging and testing units need less water, power and process maturity than a leading-edge fab and can start producing within two or three years, which is why the units already in commercial production are packaging and memory-module plants while the country's first commercial wafer fab, being built by Tata Electronics with Taiwan's Powerchip Semiconductor Manufacturing Corporation at Dholera in Gujarat, is still working towards trial production. Semicon 2.0 widens the field again by adding equipment, materials, research and talent to design, fabs and packaging.
Simple Analogy: The fab is the printing press that produces the pages; ATMP and OSAT are the bindery that turns them into a usable book. India built binderies first because presses take longest to commission.
Build a semiconductor and display ecosystem and act as the single nodal agency for implementing the sector's schemes.
Key: Launched in 2021 alongside the first SEMICON India, with a ₹76,000 crore outlay, as an independent business division within Digital India Corporation under MeitY, with administrative and financial autonomy.
Extend policy support beyond factory-building to the parts of the chain India still lacks.
Key: Approved by the Union Cabinet on 15 July 2026 with an outlay of ₹1,27,500 crore, built on six pillars — chip design, semiconductor equipment and materials, fabrication, packaging, research and development, and talent creation.
Support Indian companies designing integrated circuits, chipsets, systems on chip and IP cores rather than only manufacturing them.
Key: 24 start-ups have been approved under the scheme, and state-of-the-art design tools have been extended to more than 332 academic institutes and 105 start-ups.
Serve as the annual convergence point for the global and Indian semiconductor ecosystem, bringing in investors, policymakers, suppliers and talent.
Key: Fifth edition in 2026 at Yashobhoomi, jointly organised by ISM and SEMI, themed 'Silicon to Systems: Building the Ecosystem', with six international country roundtables and a 'Sand to Silicon to Systems' value-chain experience.
Nodal agency for the semiconductor and display schemes, and co-organiser of SEMICON India.
Parent ministry for the Semicon India Programme, the Design Linked Incentive scheme and the wider electronics manufacturing schemes.
Global industry association for the semiconductor and electronics design and manufacturing supply chain; co-organises the SEMICON series of expositions worldwide.
The venue — a Government of India convention and exhibition complex at Dwarka, New Delhi, used for large international events.
Semiconductor manufacturing depends on gallium, germanium, high-purity silicon and rare gases, tying the chip programme to the National Critical Mineral Mission and to export-control geopolitics.
The Semicon India Programme sits within the wider family of manufacturing incentives — PLI for electronics, the Design Linked Incentive for chip design, and the electronics component manufacturing scheme.
A fab consumes very large volumes of ultra-pure water and uninterrupted power, which is why the sites chosen — Dholera in Gujarat, Sanand, Jagiroad in Assam — are tied to dedicated industrial infrastructure.
Talent creation is one of Semicon 2.0's six pillars, and design tools have gone to over 332 academic institutes, connecting the mission to engineering education policy.
Chips are dual-use — defence electronics, satellites and telecom all depend on them — so domestic capability is discussed alongside defence indigenisation and telecom security rather than as pure industrial policy.
GS Paper 3 > Science and Technology > Indigenisation of technology; Economy > Industrial policy and manufacturing incentives
General Awareness > Science and technology, government schemes
General Awareness > Government schemes and industrial investment
General Awareness > Current events of national importance
Semiconductors have appeared in UPSC Prelims and Mains repeatedly since 2022 and are a standing item in banking and SSC general awareness because of the scale of the investments involved.
A semiconductor fabrication plant, where silicon wafers are patterned into chips; the most capital-intensive stage of the chain.
Assembly, Testing, Marking and Packaging — the back-end stage that turns finished wafers into usable packaged chips.
Outsourced Semiconductor Assembly and Test — an ATMP facility that performs the work on contract for other companies' chips.
The nodal agency under MeitY, set up in 2021 as an independent division of Digital India Corporation, implementing India's semiconductor and display schemes.
MeitY scheme supporting Indian semiconductor design firms and start-ups; 24 start-ups have been approved under it.
The global semiconductor and electronics industry association, with over 4,000 member companies, which co-organises SEMICON India.