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SEMICON India 2026 runs from 17 to 19 September 2026 at Yashobhoomi, Dwarka, on the theme 'Silicon to Systems: Building the Ecosystem'.
Twelve semiconductor projects have been approved across six states with investment commitments above Rs 1.64 lakh crore; three units are already in commercial production.
Semicon India 2.0, approved in July 2026, carries an outlay of Rs 1,27,500 crore against Rs 76,000 crore for the 2021 programme.
India has joined the United States-led Pax Silica coalition, which aims to secure the global silicon supply chain.
Build a full domestic semiconductor and display ecosystem rather than a single showpiece plant.
Key: Approved 15 December 2021 with Rs 76,000 crore; fiscal support of up to 50 per cent of project cost for silicon fabs, compound semiconductor units, assembly and testing plants and chip design.
Scale the 2021 foundation across the value chain.
Key: Rs 1,27,500 crore across six pillars - chip design, semiconductor equipment and materials, fabrication, advanced packaging, research and development, and talent.
Move Indian industry up the value chain from assembly into chip design.
Key: A MeitY scheme with C-DAC as nodal agency, open to applications from 1 January 2022; 24 design projects approved for financial support and 105 startups and MSMEs given EDA tool support.
Spread design capability beyond a handful of elite laboratories.
Key: Electronic Design Automation tools deployed across 320 academic institutions, with more than 68,000 students trained.
Give shared access to capital-intensive chip design tools and fabrication services.
Key: A centralised national facility set up under C2S and DLI; its users' designs go for fabrication to SCL, Mohali and to advanced foundries abroad.
Nodal agency for semiconductor and display manufacturing and for the design ecosystem; approved 15 December 2021
Premier R&D organisation of MeitY; nodal agency for the DLI Scheme and operator of the ChipIN Centre
Government-owned fabrication facility in Punjab where ChipIN-supported designs are taped out
| Aspect | Wafer fabrication (fab) | ATMP / OSAT |
|---|---|---|
| What it does | Prints circuits onto silicon wafers using lithography | Assembles, tests, marks and packages fabricated wafers into finished chips |
| Capital intensity | Highest in the chain; measured in process nodes such as 28 nm | Lower; measured in units packaged per day |
| Indian example | Tata Electronics with PSMC, Taiwan, at Dholera, Gujarat - Rs 91,000 crore, 50,000 wafer starts a month at 28 nm | Micron at Sanand, Gujarat (approved June 2023, inaugurated 28 February 2026) |
Union Cabinet approves the Semicon India programme with a Rs 76,000 crore outlay; ISM is set up under MeitY.
Design Linked Incentive Scheme opens for applications, with C-DAC as nodal agency.
Micron's assembly, test, marking and packaging unit at Sanand, Gujarat is approved.
Tata Electronics-PSMC wafer fab at Dholera (Rs 91,000 crore) and the CG Power-Renesas-Stars Microelectronics OSAT at Sanand (Rs 7,600 crore) are approved.
Kaynes Semicon's unit at Sanand, Gujarat is approved, with a project investment of about Rs 3,300 crore.
India joins the Pax Silica coalition at the India AI Impact Summit 2026.
Micron's Sanand facility is inaugurated.
Kaynes Semicon reaches commercial production, the second approved unit to do so.
Semicon India 2.0 is approved with an outlay of Rs 1,27,500 crore.
SEMICON India 2026 is held at Yashobhoomi, Dwarka.
A United States-led coalition of trusted nations - including Australia, Japan, South Korea, Singapore, the United Kingdom, Israel, the UAE and the EU - formed to secure the full 'silicon stack' from critical minerals through fabrication to AI deployment infrastructure, and to resist economic coercion and overconcentration in supply chains.
Car factories worldwide halted during the COVID-19 pandemic for want of chips rather than steel or labour, which is why semiconductors are now treated as a foundational industry on which automobiles, healthcare and defence all rest.
GS Paper 3 > Science and Technology > Indigenisation of Technology and Developing New Technology
General Awareness > Government Schemes and Economy
General Awareness > Industrial Policy and Manufacturing
The point at which a finished chip design is sent to a foundry for manufacture; 211 chips had been taped out by 75 Indian institutions by April 2026.
The nominal size of transistor features on a chip, in nanometres - the Dholera fab is planned at 28 nm, and Indian institutions have fabricated down to 12 nm.
Assembly, Testing, Marking and Packaging; Outsourced Semiconductor Assembly and Test - the back end that turns fabricated wafers into usable chips.
The full chain Pax Silica seeks to secure: critical minerals, fabrication, advanced AI systems and deployment infrastructure.