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SEMICON India 2026, the fifth edition of India's flagship semiconductor conference, concluded at Yashobhoomi, New Delhi after a three-day run from 17 to 19 September 2026 on the theme 'Silicon to Systems: Building the Ecosystem'.
The concluding session carried 15 announcements covering indigenous processors, sovereign computing, AI and quantum platforms, fab automation and skilling; across three days the event recorded 56 MoUs, announcements and strategic initiatives.
Winners of the Digital India RISC-V (DIR-V) Grand Challenge under MeitY's Chips to Startup programme were announced, with Rs 60 lakh shared by three teams building products on the indigenous SHAKTI and VEGA processors.
The Prime Minister, who inaugurated the event, virtually started commercial production lines at CDIL Semiconductor, Mohali and Suchi Semicon, Surat, taking operational units under Semicon 1.0 to five of twelve approved projects.
Semicon 2.0, with an outlay of Rs 1,27,500 crore, is structured around six pillars: design, machines and materials, new fabs, advanced packaging, research and talent development.
Build a full semiconductor and display manufacturing ecosystem in India.
Key: Approved in 2021 with an outlay of Rs 76,000 crore under MeitY. This first phase, now called Semicon 1.0, approved 12 projects, of which five are in commercial production.
Move from creating capacity to building depth across the whole value chain.
Key: Outlay of Rs 1,27,500 crore, approved by the Union Cabinet in 2026 and notified on 31 August 2026. Six pillars: design; machines and materials; new fabs; advanced packaging (ATMP/OSAT); research and development; talent development.
Support domestic fabless chip design firms and start-ups with design infrastructure and staged incentives.
Key: Launched December 2021 as a component of the Semicon India Programme; participants get access to Electronic Design Automation (EDA) tools and incentives across the design, deployment and production stages.
Build chip-design manpower and turn academic designs into products.
Key: MeitY programme launched in 2022 across 113 institutions; targets 85,000 VLSI and embedded-system design engineers, 175 ASICs, 20 working System-on-Chip prototypes and an IP core repository over five years. The DIR-V Grand Challenge and the Bharat AI-SoC Challenge run under it.
Make India a supplier, not just a user, of processor designs by building on the open RISC-V instruction set.
Key: Launched by MeitY in 2022; anchored on the indigenous SHAKTI processors of IIT Madras and the VEGA processors of C-DAC.
Seed and scale India's quantum computing, communication, sensing and materials research.
Key: Approved by the Cabinet on 19 April 2023 with an outlay of Rs 6,003.65 crore for 2023-24 to 2030-31, implemented by the Department of Science and Technology; targets quantum computers of 50-1,000 physical qubits in eight years. C-DAC's PARAM Shavak-QS quantum simulation platform sits in this ecosystem.
Nodal agency driving India's semiconductor and display manufacturing strategy and administering the Semicon India schemes.
MeitY's R&D organisation for advanced computing; developer of the PARAM supercomputer series and the indigenous VEGA processors. Announced tie-ups with NLC India and Bharat Electronics Limited for indigenous data centres and sovereign high-performance computing.
India's government-owned fab, supplying chips for strategic and space applications; launched DMIS for wafer-fabrication management.
MeitY's skilling body; announced ATMP skilling and a Digital Twin for Semiconductor Manufacturing, including an upcoming ATMP facility at Guwahati.
Developed the SHAKTI family of RISC-V processors, used by the first-prize DIR-V entry.
RISC-V is an open, royalty-free processor instruction set: anyone may build a chip on it without licensing it from a company, unlike x86 or ARM. ATMP - Assembly, Testing, Marking and Packaging - is the back-end stage where finished wafers are cut, packaged and tested into usable chips.
Simple Analogy: RISC-V is an open grammar anyone may write in; ATMP is the binding and proofing of the printed book.
C-DAC established, initially to develop supercomputers indigenously.
Semicon India Programme approved with a Rs 76,000 crore outlay; India Semiconductor Mission set up within Digital India Corporation.
Design Linked Incentive scheme launched for fabless design firms and start-ups.
Chips to Startup programme and the Digital India RISC-V programme launched by MeitY.
Cabinet approves the National Quantum Mission, Rs 6,003.65 crore for 2023-24 to 2030-31.
Semicon 2.0 notified with a Rs 1,27,500 crore outlay and a six-pillar structure.
SEMICON India 2026 held at Yashobhoomi; 56 MoUs and announcements; five Semicon 1.0 units now in commercial production.
The C-DAC tie-ups with BEL and NLC India are about indigenous high-performance computing and data centres - the hardware side of the same argument that drives data-localisation and digital-sovereignty policy.
RISC-V matters to India for the reason UPI and ONDC did: an open specification avoids dependence on a foreign licensor, and licence costs do not scale with volume.
Semiconductors are a working agenda item in the Quad and in India's bilateral technology initiatives; the six Country Roundtables at SEMICON mirror that diplomacy.
GS Paper 3 > Science and Technology > Indigenisation of Technology and Developing New Technology
General Awareness > Government Schemes and Science & Technology
General Awareness > Industrial Policy and Manufacturing Incentives
Semiconductor policy has recurred in exam-oriented current affairs every year since 2022
An open, royalty-free instruction set architecture that anyone may use to design a processor without paying a licence fee.
Assembly, Testing, Marking and Packaging; an OSAT is an Outsourced Semiconductor Assembly and Test provider doing that work for others.
A company that designs chips but has them manufactured by an external foundry rather than owning a fabrication plant.
A semiconductor fabrication plant where silicon wafers are processed into integrated circuits.