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The Prime Minister inaugurated the fifth edition of SEMICON India at Yashobhoomi, New Delhi on 17 September 2026, themed 'Silicon to Systems: Building the Ecosystem' and running to 19 September.
Semicon 2.0, approved by the Union Cabinet on 15 July 2026 with an outlay of Rs 1,27,500 crore, widens the mission from fabs and packaging to six pillars covering design, equipment and materials, advanced packaging, applied R&D and talent.
Investment commitments of about Rs 1 lakh crore have been received and close to 1 lakh jobs are expected across the ecosystem over the next two to three years.
Commercial lines were launched at CDIL Semiconductor, Mohali and Suchi Semicon, Surat, taking operational commercial ATMP units to five of the twelve approved under Semicon 1.0.
Build the complete chip value chain in India rather than only its closing stages, covering materials and equipment through to finished chips.
Key: Outlay Rs 1,27,500 crore; targets 200 design start-ups and training of 1 lakh technicians over five years, with partners including ITRI, Taiwan.
Create a domestic semiconductor and display manufacturing ecosystem from a standing start.
Key: Outlay Rs 76,000 crore, with separate schemes for fabs, display fabs, compound semiconductors and ATMP-OSAT units. Of the twelve units approved, one is a silicon fab, one a silicon carbide fab, one a Gallium Nitride Micro LED display fab and nine are ATMP/OSAT.
Support Indian chip-design start-ups and MSMEs across design, deployment and productisation.
Key: Launched under the Semicon India Programme by MeitY with C-DAC as nodal implementing agency; 24 chip design projects worth about Rs 900 crore approved.
Build chip-design manpower by giving academic institutions and start-ups access to advanced design and prototyping tools.
Key: MeitY scheme with C-DAC as nodal agency; over 1 lakh engineers from 500 organisations, including 400 academic institutions and 100 start-ups, have been given advanced chip-design tools, producing over 300 chip designs.
Create the demand base and component depth a fab ecosystem needs.
Key: National Policy on Electronics 2019 (ESDM framework); SPECS 2020 (25 per cent capex incentive); EMC 2.0 2020 (plug-and-play infrastructure); PLI for Large Scale Electronics 2020 and PLI 2.0 for IT Hardware 2023.
Nodal agency for the Semicon India Programme, with autonomy over fab, display, packaging and design strategy
Government fab supplying radiation-hardened, flight-grade devices to ISRO missions
Nodal implementing agency for the DLI Scheme and the Chips to Startup Programme
Global industry association of the electronics design and manufacturing supply chain; organises the SEMICON events
Semicon India Programme (Semicon 1.0) approved with Rs 76,000 crore; ISM set up 15 December.
Micron's Sanand ATMP unit becomes the first proposal approved under the India Semiconductor Mission.
India and Germany sign a Joint Declaration of Intent on a Semiconductor Ecosystem Partnership.
India joins Pax Silica at the India AI Impact Summit.
Union Cabinet approves Semicon 2.0 with Rs 1,27,500 crore.
SEMICON India 2026 inaugurated; commercial lines launched at CDIL Mohali and Suchi Semicon Surat; 11 MoU exchanges and announcements.
A node names a generation of manufacturing technology. Labels such as 90 nm or 28 nm once tracked a physical dimension; today they are shorthand for a process generation. Smaller nodes can raise density or cut energy use, but mature nodes remain essential for automobiles and power systems.
Simple Analogy: Like engine generations in cars: the name signals a family, not one measurement.
GS Paper 3 > Science and Technology > Indigenisation of Technology and Developing New Technology
General Awareness > Schemes and Current Affairs
General Awareness > Government Schemes and Economy
Assembly, Testing, Marking and Packaging - the back-end stage after wafer fabrication, where a chip is packaged, tested and marked.
Outsourced Semiconductor Assembly and Test - a third-party firm performing ATMP work for chipmakers.
A firm that designs chips but outsources their manufacture to a foundry.
The point at which a completed chip design is sent for production.