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Aheesa Digital Innovations, a Chennai-headquartered fabless startup supported under the Design Linked Incentive Scheme, has achieved first-pass silicon success with 'VIHAAN', a networking System-on-Chip built for fibre broadband using the indigenous VEGA microprocessor.
VIHAAN was taped out on Republic Day and reached first-pass silicon on Independence Day this year; production tape-out is targeted for 2027.
The company raised about ₹40 crore earlier this year from the Tamil Nadu Infrastructure Fund Management Corporation through the Tamil Nadu Emerging Sector Seed Fund, alongside private investors.
Companies supported under the DLI Scheme have collectively achieved more than 30 chip-design tape-outs and raised over US$100 million in venture funding; under the Chips to Startup programme, 245 designs have been taped out by 71 academic institutions.
Chip-design tools have been made available to 455 organisations — 350 academic institutions and 105 startups — and the release places semiconductor design at up to 50 per cent of value addition across the semiconductor chain.
Three terms in this release carry the whole story. A 'tape-out' is the moment a finished chip design is handed to a foundry for fabrication — the name survives from the era when the design was delivered on magnetic tape. 'First-pass silicon' means the fabricated chip works correctly on the first attempt, without a redesign-and-refabricate cycle. That distinction is expensive rather than merely technical: a single advanced-node mask set and fabrication run can cost crores, and a failed first pass adds months and another full run. Achieving first-pass silicon is therefore the standard industry proof that a design team is mature. 'Fabless' describes a company such as Aheesa that designs chips but owns no fabrication plant, contracting manufacture to a foundry — the dominant model worldwide, and the model India's design-side incentives are built around. Note the sequencing in this case: the engineering tape-out that validated the design has happened, but the production tape-out that begins commercial manufacture is targeted only for 2027.
Simple Analogy: A tape-out is sending the final blueprint to the builder. First-pass silicon is the building passing inspection with no rework needed — cheap to say, very expensive to fail.
Offset the disadvantages faced by India's domestic semiconductor design industry by supporting startups, MSMEs and academia from concept through to silicon.
Key: Announced by the Ministry of Electronics and Information Technology and launched in December 2021 as part of the Semicon India Programme. The Centre for Development of Advanced Computing (C-DAC) is the nodal implementing agency. Support covers financial incentives, access to advanced design tools and prototyping, and spans applications from satellite communications and drones to automotive, IoT, LED drivers, AI systems, telecom equipment and smart meters.
Build the chip-design workforce by embedding design projects in academic institutions.
Key: An umbrella capacity-building programme of MeitY aimed at generating around 85,000 industry-ready professionals at B.Tech, M.Tech and PhD levels. Under it, 245 chip designs have been taped out by 71 academic institutions — a figure worth holding alongside the DLI numbers, because C2S produces people while DLI produces products.
Build a complete semiconductor ecosystem covering design, fabrication, advanced packaging, equipment, materials, R&D and skilled manpower.
Key: The India Semiconductor Mission was approved in December 2021 with a ₹76,000 crore incentive framework under MeitY, offering fiscal support of up to 50 per cent of project cost. Its second phase, Semicon 2.0, was approved in July 2026 with an outlay of ₹1,27,500 crore.
Develop indigenous microprocessors on the open RISC-V instruction set architecture.
Key: Launched by MeitY in 2022 under the Aatmanirbhar Bharat framework. Its two flagship processor families are VEGA, developed by C-DAC, and SHAKTI, developed by the RISE group at IIT Madras. RISC-V matters here because it is an open, royalty-free instruction set — a design house using it does not need a licence from a foreign architecture owner, which is the whole strategic point of building VIHAAN on VEGA.
MeitY's premier R&D organisation for advanced computing; nodal implementing agency for the DLI Scheme and developer of the VEGA processor family.
Owns the Semicon India Programme, the India Semiconductor Mission, the DLI Scheme, the C2S Programme and the DIR-V Programme.
The Government's own fabrication facility, where the 64-bit THEJAS64 VEGA processor was fabricated on a 180 nm process — relevant context for how far indigenous silicon has been taken.
The state-promoted fund manager that invested about ₹40 crore in Aheesa through the Tamil Nadu Emerging Sector Seed Fund — an example of state-level capital entering deep tech alongside central incentives.
RISC-V is open and royalty-free, unlike the proprietary architectures that dominate commercial processors. Building a national processor family on it means Indian designers can modify the core and ship products without a foreign architecture licence — which is why DIR-V, VEGA and SHAKTI are treated as strategic rather than merely technical programmes.
The ₹76,000 crore India Semiconductor Mission targets fabs and packaging plants — capital-heavy, slow, and geographically concentrated. The DLI Scheme targets design — capital-light, faster, and distributed across startups and campuses. India's strategy runs both, and the exam distinction is that DLI is implemented through C-DAC while fab incentives run through the India Semiconductor Mission.
A networking SoC built for fibre broadband connects directly to India's optical fibre rollout, including BharatNet's gram panchayat connectivity and the 5G backhaul build-out — domestic demand is what makes a domestically designed broadband chip commercially viable.
TNIFMC's investment through a state seed fund shows sub-national governments financing semiconductor startups alongside central incentives, a pattern also visible in state semiconductor policies in Gujarat, Uttar Pradesh and Odisha.
GS Paper 3 > Science and Technology: Indigenisation of Technology and Developing New Technology
General Awareness > Science and Technology and Government Schemes
General Awareness > Government Schemes and Industrial Policy
General Awareness > Science and Technology
Semiconductor policy and indigenous processors have appeared repeatedly in UPSC Prelims and Mains since 2022 and are a recurring science-and-technology theme in all major examinations.
The handing over of a completed chip design to a foundry for fabrication; an engineering tape-out validates the design, a production tape-out begins commercial manufacture.
A fabricated chip that functions correctly on its first manufacturing run, with no redesign cycle required.
A firm that designs semiconductors but owns no fabrication plant, outsourcing manufacture to a foundry.
A single chip integrating processor, memory, input-output and other subsystems that would otherwise sit on separate components.
An open, royalty-free instruction set architecture; the basis of India's DIR-V programme and of both the VEGA and SHAKTI processor families.
An architecture that performs computation inside the memory array to cut the energy cost of moving data, used in one of the other DLI results reported alongside VIHAAN.